Description

If I perform a behavioral simulation of a register without reset logic connected to it, the output of the register is in an undetermined state and is represented by a red 'X'.

If I perform a post-Synthesis/Translate/MAP/PAR simulation, the register is reset by the global reset signal, and outputs the desired state.

How do I model the global resetcircuit behavior infunctional simulation?

An example circuit showing this behavior is shown below:

reg [11:0] CLK_CNT;
always@(posedge SYS_CLK)begin
CLK_CNT <= CLK_CNT +1;
end

Solution

In behavioral simulation, use either of the following ways to specify the initial/reset value of a register:

• Use local reset signal to reset the register.

reg [11:0] CLK_CNT;

always@(posedge SYS_CLK)

begin

if (reset)

CLK_CNT <= 12'd0;

else

CLK_CNT <= CLK_CNT +1;

end

• Describe a GSR pulse behavior and use the GSR pulse to reset the register.

NOTE: This isnota recommended way.

• Assign an initial value to the register when declare the reg type

reg [11:0] CLK_CNT = 12'd0;

always@(posedge SYS_CLK)

begin
CLK_CNT <= CLK_CNT +1;

end

In the Gate-level (post-Synthesis/Translate/MAP/PAR) simulation, the GSR behavior is described in the simulation models in unisims/simprims. So, if you do not have reset logic on the register, nor specify the initial value, the GSR signal resets the registers to the default initial value 0 in the Gate-level simulation. However, in the behavioral simulation, GSR does not affect theregisters if you do not describe it in your own code. Therefore, you need to explicitly specify the initial value if there is no local reset logic on the register.