Version Found: 1.00.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)
The Virtex-6 AXI EP Bridge for PCI Express must use the 64-bit AXI data width. When mastering on an AXI-lite interconnect with a 64-bit AXI data width, the bridge sets the burst size to 8-bytes instead of 4-bytes when there isan incoming 1 d-word memory read or write request. This causes the an error as indicated in (Xilinx Answer 43491).
NOTE:The "Version Found" columnlists the version that the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.
The AXI EP Bridge v1.00a for PCI Express has a known issue when mastering onto a 32-bit AXI interconnect. The AXI-lite interconnect data width only supports as 32-bit, which does notallow the bridge to master on the AXI-lite interconnect. The files provided will allow the bridge to create 4-byte burst size transactions on the AXI interconnect when a 1 d-word packet comes in from the upstream component.
To work around this issue, perform the following steps:
11/21/2011 -Updated for13.3
08/30/2011 - Initial Release