General Description: How do I instantiate components from the Xilinx Unified Library in my HDL?
All Xilinx primitives can be instantiated in a design that is to be synthesized by FPGA Express. Use the Xilinx Libraries Guide to find the names of the pins.
For Xilinx macros, add the appropriate XNF file to your project. XNF files can be obtained from the $SYNOPSYS\xilinx\macros\<family>\v6_xnf directory, where $SYNOPSYS is the Synopsys install directory for FPGA Compiler II users, and the %XILINX%\express directory for Foundation users. Macros are only available for 3K and 5200 series families.
NOTE #1: Bus pins are not delimited with brackets (i.e. BUS<3>) within these macro XNF files; there are no delimiters (i.e. BUS3). Therefore, before reading a macro XNF into your FPGA Express project, select Synthesis -> Options and select the "Project" tab. Change the "Input XNF Bus style" to %s%d instead of %s<%d>.
NOTE #2: This solution does not apply to Virtex/E or Spartan-II designs, as macros for these devices are not available. Moreover, FPGA Express 3.3 and earlier do not recognize primitives. Please see (Xilinx Solution 6987) for complete details.