This answer record provides a downloadable MIG 7 Series DDR3/DDR2 Hardware Debug Guide in PDF format to enhance its usability.
Answer records are Web-based content that are frequently updated as new information becomes available. Visit this answer record to obtain the latest version of the PDF.
Note: Starting with the release of MIG 7 Series v1.9, this debug content has been moved to the 7 Series FPGAs Memory Interface Solutions User Guide. Please reference the "Debugging DDR3/DDR2 Designs" section.
Note: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243).
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Please download the 7 Series MIG DDR3/DDR2 Hardware Debug Guide (PDF) attached to the end of this solution.
This document describes techniques to debug calibration failures and data errors related to designs using the 7 series MIG DDR3 SDRAM core.
A complete list of signals to capture in the ChipScope Pro tool when debugging calibration failures and data errors has been provided.
ChipScope Pro tool screen captures illustrate how to analyze those signals and establish theories on potential root causes.
Please use the 7 series Calibration Results spreadsheet (ar43879_7series_ddr3_cal_results.xlsx), attached to the end of this solution, to capture the results.
03/11/2014 - Updated tap collection spreadsheets to latest calibration algorithm
04/29/2013 - Added note that the debug content is now part of the user guide.
10/12/2012 - Updated attachments.
10/05/2012 - Added PRBS Read Leveling, Traffic Generator Data Error Debug, and Window Margin Check.
07/19/2012 - Added content to Data Error Debug sections.
06/04/2012 - Updated CK to DQS Trace Matching Guidelines and added content to Isolating Data Errors section.
05/08/2012 - Initial release.