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AR# 43937

System Generator for DSP - Why the output of FIR Compiler are all zeros?

Description

When the EN of a Finite Impulse Response (FIR) compiler is not constant 1 or is 1 every other cycle, the output of the FIR Compiler is zero.

What is the cause of this issue?

Solution

This issue occurs when FIR Compiler type is decimation and EN is used. 

When the output rate of FIR Compiler is <= EN(clock enable). The system enable for output and enable for FIR Compiler will not be aligned. 

The final enable to output data will be zero all the time.

To work around the problem, use ND instead to control the din of FIR Compiler or generate FIR Compiler from coregen, then add it as a black box to the design.

From 2013.1 System Generator will produce the following warning:

Clock enable is present for a rate changing configuration. User has to ensure that the clock enable is aligned with internally generated clock enables for correct operation.
Please consult the section on "Clock Handling in HDL" from System generator user guide.
Support for user driven clock enables for rate changing configurations may be deprecated in future.

AR# 43937
Date Created 09/06/2011
Last Updated 09/02/2014
Status Active
Type General Article
Tools
  • System Generator for DSP
IP
  • FIR Compiler