AR# 43989

Description

Can 7 Series High Range (HR) I/O banks be powered at 3.3V or support the LVDS_33 I/O standard?

Can UltraScale / UltraScale+ High Density (HD) I/O banks be powered at 3.3V or support the LVDS_33 I/O standard?

If using a LVDS_33 output on an older Spartan family, is it possible to connect this differential signal into:

• A 7 series HR I/O bank differential pin pair?
• A 7 series HP I/O bank differential pin pair?
• An UltraScale or UltraScale+ HD I/O bank differential pin pair?
• An UltraScale or UltraScale+ HP I/O bank differential pin pair?

Can LVDS inputs be used in an HP I/O bank that is not powered at 1.8V?

Can LVDS_25 inputs be used in an HR or HD I/O bank that is not powered at 2.5V?

Solution

3.3V LVDS:

• The "LVDS_33" I/O Standard that was available in some older FPGA families, is not supported in 7 Series, UltraScale or UltraScale+ devices.
• Neither High Range (HR) banks, High Density (HD) banks, nor High Performance (HP) banks can have their VCCO pins powered at 3.3V (if using LVDS outputs).
• Older families' LVDS_33 outputs might be supportable in the 7 Series, UltraScale and UltraScale+ I/O banks, but care must be used to ensure that:

1. Vin in Table 1 and 2 of the Data Sheet is not violated.
2. VIDIFF and VICM for LVDS (HP banks) or LVDS_25 (HR or HD banks) is not violated.
   

Running signal integrity simulations using IBIS models might be required in order to insure that those two items are not violated.

Using LVDS or LVDS_25 inputs when the VCCO is not set to the proper voltage level:

1. The DIFF_TERM attribute must be FALSE - you will need to use an external differential termination resistor.
2. Ensure that the VOD and VOCM levels of the driving device fall within the range of VIDIFF and VICM of the 7 Series, UltraScale or UltraScale+ receiver, and that the VIN in Table 1 and 2 of the data sheet are not violated.
   
   

Table 1-55: "VCCO and VREF Requirements for Each Supported I/O Standard" in the 7 Series FPGAs SelectIO Resources User Guide (UG471) outlines the VCCO and VREF voltage rail requirements for all of the supported I/O standards, with different columns for inputs vs. outputs (bidirectional pins would need to adhere to both).

Table 1-77: "VCCO and VREF Requirements for Each Supported I/O Standard" in the UltraScale Architecture SelectIO Resources User Guide (UG571) outlines the VCCO and VREF voltage rail requirements for all of the supported I/O standards, with different columns for inputs vs. outputs (bidirectional pins would need to adhere to both).

LVDS Interface Checklist:

If you are interfacing via LVDS you can follow the steps in the flow charts below to ensure that you meet all of the requirements for correct LVDS usage.

hp_checklist.PNG

hr_checklist.PNG

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