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Can 7 series High Range (HR) I/O banks be powered at 3.3V or support the LVDS_33 I/O standard?
If using a LVDS_33 output on an older Spartan family, is it possible to connect this differential signal into:
Can LVDS inputs be used in an HP I/O bank that is not powered at 1.8V?
Can LVDS_25 inputs be used in an HR I/O bank that is not powered at 2.5V?
3.3V LVDS:
Running signal integrity simulations using IBIS or HSPICE models may be required in order to insure that those two items are not violated.
Using LVDS or LVDS_25 inputs when the VCCO is not set to the proper voltage level:
It is acceptable to have LVDS inputs in HP I/O banks even if the VCCO level is not 1.8V. LVDS outputs (and therefore bidirectional LVDS) can only be used in a bank powered at 1.8V.
Similarly, it is acceptable to have LVDS_25 inputs in HR I/O banks even if the VCCO level is not 2.5V. LVDS_25 outputs (and therefore bidirectional LVDS_25) can only be used in a bank powered at 2.5V.
However, the following must be true:
Table 1-55 in the 7 Series FPGAs SelectIO Resources User Guide (UG471) outlines what the VCCO and VREF voltage rail requirements are for all of the supported I/O standards, with different columns for inputs vs. outputs (bidirectional pins would need to adhere to both).
LVDS Interface Checklist:
If you are interfacing via LVDS you can follow the steps in the flow charts below to ensure you meet all the requirement for correct LVDS usage.
AR# 43989 | |
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Date | 10/14/2014 |
Status | Active |
Type | General Article |
Devices |
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