AR# 43989

7 Series FPGAs - LVDS_33, LVDS_25, LVDS_18, LVDS inputs & outputs for High Range (HR) and High Performance (HP) I/O banks


Can 7 series High Range (HR) I/O banks be powered at 3.3V or support the LVDS_33 I/O standard?

If using a LVDS_33 output on an older Spartan family, is it possible to connect this differential signal into:

    • a 7 series HR I/O bank differential pin pair?
    • a 7 series HP I/O bank differential pin pair?

Can LVDS inputs be used in an HP I/O bank that is not powered at 1.8V?

Can LVDS_25 inputs be used in an HR I/O bank that is not powered at 2.5V?


3.3V LVDS:

  • The "LVDS_33" I/O Standard that was available in some older FPGA families, is not supported in 7 series.
  • Neither High Range (HR) banks, nor High Performance (HP) banks can have their VCCO pins powered at 3.3V (if using LVDS outputs).
  • Older families LVDS_33 outputs may be supportable in the 7 series I/O banks, but care must be used to ensure that:

    Running signal integrity simulations using IBIS or HSPICE models may be required in order to insure that those two items are not violated.

    1. Vin in Table 1 and 2 of the Data Sheet is not violated.
    2. VIDIFF and VICM for LVDS (HP banks) or LVDS_25 (HR banks) is not violated.

Using LVDS or LVDS_25 inputs when the VCCO is not set to the proper voltage level:

It is acceptable to have LVDS inputs in HP I/O banks even if the VCCO level is not 1.8V.  LVDS outputs (and therefore bidirectional LVDS) can only be used in a bank powered at 1.8V.
Similarly, it is acceptable to have LVDS_25 inputs in HR I/O banks even if the VCCO level is not 2.5V.  LVDS_25 outputs (and therefore bidirectional LVDS_25) can only be used in a bank powered at 2.5V.

However, the following must be true:

  1. The DIFF_TERM attribute must be FALSE - meaning, you will need to use an external differential termination resistor.
  2. Ensure that the VOD and VOCM levels of the driving device fall within the range of VIDIFF and VICM of the 7 series receiver, and that the VIN in Table 1 and 2 of the data sheet are not violated.


Table 1-55 in the 7 Series FPGAs SelectIO Resources User Guide (UG471) outlines what the VCCO and VREF voltage rail requirements are for all of the supported I/O standards, with different columns for inputs vs. outputs (bidirectional pins would need to adhere to both).


LVDS Interface Checklist:

If you are interfacing via LVDS you can follow the steps in the flow charts below to ensure you meet all the requirement for correct LVDS usage. 






AR# 43989
Date 10/14/2014
Status Active
Type General Article
Devices More Less