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This article describes the restrictions on the TXOUTCLK and RXOUTCLK ports of the transceiver. To cope with these restrictions, the MMCM transmitter input now comes from the reference clock, IBUFDS_GTE2. And, the transceiver TXOUTCLK port is disabled. The receiver side clocking remains unchanged. You must also set the TXOUTCLKSEL input to the GTXE2_CHANNEL instance to "000".
Figure 1 shows the revised clocking scheme.
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For the LogiCORE CPRI Release Notes and Known Issues, see (Xilinx Answer 36969).
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
36969 | LogiCORE IP CPRI - Release Notes and Known Issues | N/A | N/A |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
44215 | 7 Series Integrated Wrapper for LogiCORE CPRI - v4.1- Should the transceiver transmit and receive elastic buffers be enabled? | N/A | N/A |
44011 | 7 Series Integrated Wrapper for LogiCORE CPRI - IBUFDS_GTE2 Use Model Change | N/A | N/A |
43339 | 7 Series FPGA GTX Transceiver - Software Use Model Changes | N/A | N/A |
43244 | Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon | N/A | N/A |
AR# 44012 | |
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Date | 05/22/2012 |
Status | Archive |
Type | Known Issues |
IP |
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