Description

Version Found: 1.00.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)

TheAXI Bridge for PCI Express might not accept incoming TLPs when the endpoint's BARs are configured as 64-bit (C_PCIEBAR_AS = '1').This issue is exclusive to the 64-bit AXI data width and does not apply to the 32-bit or the 128-bit AXI data width.Furthermore, this issue only occurs when there are multiple BARs configured within the bridge and the host configures one of the upper BARs as 32-bit.

TheAXI Bridge for PCI Expresscurrently supports 3 BARs regardless if they are configured as 32 or 64-bit.According to the PCI Express specification, an endpoint supports 6 BARs when they are 32-bit.When a BAR is configured as 64-bit, it uses two 32-bit BARs. When theAXI Bridge for PCI Express configures its BARs as 64-bit, it uses BAR0 and BAR1 of the type 0 configuration space for the first BAR of the bridge. The second BAR uses BAR2 and BAR3 of the configuration space. Lastly, the third BAR of the bridge uses BAR4 and BAR5 of the configuration space.

The issue occurs when there are two or three 64-bit BARs and the second or third BAR are configured as 32-bit BARs. Even though a BAR is set up as 64-bit BAR, the host can set up a BAR as 32-bit if the enumerated address range results below 4GB. This is per section 2.2.4.1 of the PCI Express specification.

NOTE:The "Version Found" columnlists the version that the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.

Solution

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