This section of the MIG Design Assistant focuses on the MIG generated output for Spartan-6 FPGA DDR3/DDR2 designs. The MIG output includes RTL files for the MIG core, an example traffic generator, simulation testbench with the appropriate memory model instantiated, simulation and implementation script files, and a User Constraints Files (.ucf).These files allow users to quickly simulate the design to view functional behavior and create a bit file to run the design in hardware. Select from the options below to find information related to your specific question.
NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.