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AR# 44096

MIG Spartan-6 FPGA DDR2/DDR3 - Output Directory/File Descriptions

Description

This section of the MIG Design Assistant focuses on the output directory structure and generated files for Spartan-6 FPGA DDR3/DDR2 designs. Below you will find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

For a description of the output directory structure and files for Spartan-6 FPGADDR3/DDR2 designs, please see the "Getting Started" -> "Directory Structure and File Descriptions" section in the Spartan-6 FPGA Memory Interface Solutions User Guide (UG416). This document can be found here:
http://www.xilinx.com/support/documentation/ipmeminterfacestorelement_meminterfacecontrol_mig-v6.htm.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
44095 MIG Spartan-6 FPGA DDR2/DDR3 - MIG Output N/A N/A
AR# 44096
Date Created 11/15/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
IP
  • MIG Virtex-6 and Spartan-6