AR# 44109

UG534 - GTX QUAD_115 reference clock connections are swapped in Figure 1-10

Description

Fig. 1-10 of UG534, ML605 Hardware User Guide (v1.6), shows a 100 MHz LVDS clock connected to REFCLK1 of GTX QUAD_115. However, the ML605 schematics show the 100 MHz LVDS clock as connected to the REFCLK0 pins. Which is correct?

Solution

The connection shown in the ML605 schematics is the correct one. The 100 MHz LVDS clock of GTX QUAD 115 is connected to REFCLK0, not REFCLK1. This will be corrected in the next release of UG534, ML605 Hardware User Guide.
AR# 44109
Date 10/17/2011
Status Active
Type Documentation Changes