AR# 4413


ModelSim (MXE, SE, PE) - "ERROR (line number): "Subprogram is ambiguous" or "use '-explicit' option to disable" (VHDL)"


General Description:

When I compile a VHDL file in ModelSim, the following error message occurs:

"ERROR: <file>.vhd (line number): Subprogram "=" is ambiguous. Suitable

definitions exist in package 'std_logic_1164' and 'std_logic_unsigned'."

"ERROR: <file>.vhd (line number): (Use the '-explicit' option to disable the previous

error check)"


This occurs because the function is being defined in two libraries. Use the "-explicit" option to resolve the function. The "-explicit" option specifies to ignore an error in packages supplied by other EDA vendors; it directs the compiler to resolve ambiguous function overloading in favor of the explicit function definition.

Command Line Example

vcom -explicit <filename>.vhd

Setting this Option in the ModelSim GUI

1. Open the compilation window by clicking "Compile".

2. Click Default Options.

3. Select the VHDL tabulation.

4. Check the box to "Use explicit declaration only".

5. Click Apply.

AR# 4413
Date 12/15/2012
Status Active
Type General Article
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