There have been reports of two designs implemented in the Virtex-4 and Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC blocks erroneously appending the end of some transmitted frames with an additional byte.
This byte is a duplication of the final byte of the Frame Check Sequence (FCS).
If this rare issue is encountered, erroneous operation might not be consistent across multiple devices or bitstreams, might not be consistent between power or reset cycles for a given combination of device and bitstream, and will not affect every transmitted frame.
This issue is limited to the following Ethernet MAC configurations:
Xilinx has developed logic which can be integrated into the Virtex-4 or Virtex-5 FPGA Ethernet MAC wrapper to correct the erroneous behavior.
It resides on the PHY-side transmit path, and checks each frame for duplication of the final FCS byte.
If duplication occurs, it corrects the transmit enable signaling to exclude the duplicated byte from the frame.
If you are using an older version of XPS_LL_TEMAC core in an earlier release, please upgrade to v2.03.a of the core available in EDK 12.x.
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