is not declared">


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AR# 44164

MIG Spartan-6 MCB DDR2 SDRAM - ERROR:HDLCompiler:69 - "mig_38\example_design\rtl\example_top.vhd" Line 789: is not declared


When synthesizing a MIG 3.8 generated VHDL Spartan-6 MCB DDR2 example design, the following errors occur:

ERROR:HDLCompiler:69 - "mig_38\example_design\rtl\example_top.vhd" Line 789: is not declared.
ERROR:HDLCompiler:69 - "mig_38\example_design\rtl\example_top.vhd" Line 791: is not declared.
ERROR:HDLCompiler:69 - "mig_38\example_design\rtl\example_top.vhd" Line 794: is not declared.
ERROR:HDLCompiler:69 - "mig_38\example_design\rtl\example_top.vhd" Line 796: is not declared.
ERROR:HDLCompiler:854 - "mig_38\example_design\rtl\example_top.vhd" Line 131: Unit ignored due to previous errors.
VHDL file mig_38\example_design\rtl\example_top.vhd ignored due to errors


This only affects VHDL MCB DDR2 designs generated in Bank3. If this error occurs, locate the following code in the example_design.vhd module:

bigger_device: if (C1_SMALL_DEVICE = "FALSE") generate
-- Drive data mode through VIO core for bigger devices
c1_vio_data_mode_value <= c1_vio_out(5 downto 3);
end generate;

small_device: if (not(C1_SMALL_DEVICE = "FALSE")) generate
-- Drive a constant data mode value for smaller devices
c1_vio_data_mode_value <= "010";

Change all instances of 'c1' to 'c3'.

This issue is resolved in MIG 1.3 available with ISE Design Suite13.3.

AR# 44164
Date 05/19/2012
Status Active
Type Known Issues
  • Spartan-6 LX
  • Spartan-6 LXT
  • MIG Virtex-6 and Spartan-6
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