The CLB SRLs and CLB/IOB D flip-flops (DFF) in FPGA fabric are, and have always been, released in all devicesusing the GWE (global write enable) signal as part of the startup sequence.As a reminder, the userclocks used in a design are asynchronous to the configuration clock (CCLK). This allows those synchronous elements to possiblychange state after configuration.
GWE releases SRLs andflip-flops synchronously to the configuration clock and has always had a significant skew across the part. Consequently, two types of behaviors are occasionally observed in a synchronous design. Xilinx is highly confident that the vast majority of designs will not be affected.
If the design meets one of the criteria below, the solution at the bottom of this answer record should be implemented in the design to prevent the possibility of this behavior from occurring:
This behavior is not new,and is consistent across all FPGA device families.To properly initialize the SRLs and flip flops, it is recommended to always use one of the solutions below.
Two different techniques can be used to ensure that the design comes out of startup synchronously to the user's system clock.
1)The first methodinvolves controlling the clocks driving the SRL and D flip-flop.
2) An alternative method uses theCE ports of individual synchronous elements which can be controlled instead of stopping the clock.
Both techniques can be used as appropriate.
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
42946 | Design Advisory Master Answer Record for Kintex-7 FPGA | N/A | N/A |
42944 | Design Advisory Master Answer Record for Virtex-7 FPGA | N/A | N/A |
34856 | Design Advisory Master Answer Record for Spartan-6 FPGA | N/A | N/A |
34565 | Design Advisory Master Answer Record for Virtex-6 FPGA | N/A | N/A |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
46791 | Spartan-6 FPGA Design Assistant - Troubleshoot Common Fabric Problems | N/A | N/A |
34856 | Design Advisory Master Answer Record for Spartan-6 FPGA | N/A | N/A |
34565 | Design Advisory Master Answer Record for Virtex-6 FPGA | N/A | N/A |
42946 | Design Advisory Master Answer Record for Kintex-7 FPGA | N/A | N/A |
42944 | Design Advisory Master Answer Record for Virtex-7 FPGA | N/A | N/A |