Description

The CLB SRLs and CLB/IOB D flip-flops (DFF) in FPGA fabric are, and have always been, released in all devicesusing the GWE (global write enable) signal as part of the startup sequence.As a reminder, the userclocks used in a design are asynchronous to the configuration clock (CCLK). This allows those synchronous elements to possiblychange state after configuration.

GWE releases SRLs andflip-flops synchronously to the configuration clock and has always had a significant skew across the part. Consequently, two types of behaviors are occasionally observed in a synchronous design. Xilinx is highly confident that the vast majority of designs will not be affected.

• Timing violations can occur with flip-flops and SRLssince GWE is releasing synchronous elements with respect to the configuration clock instead of the user's system clock.
• Propagation of the GWE signal means SRLs and flip-flops might be released at slightly different times which results in some parts of the designstarting up before others.

If the design meets one of the criteria below, the solution at the bottom of this answer record should be implemented in the design to prevent the possibility of this behavior from occurring:

• The design relies upon synchronous startup of initialized sequential elements and uses flip-flops and SRLs (this includes inferred SRLs with initial values, check the map report to determine if SRLs are used in the design).
• The design relies upon synchronous startup of initialized sequential elements and the design does not assert a reset to synchronous elements after startup. SRLs cannot be reset.

This behavior is not new,and is consistent across all FPGA device families.To properly initialize the SRLs and flip flops, it is recommended to always use one of the solutions below.

Solution

Two different techniques can be used to ensure that the design comes out of startup synchronously to the user's system clock.

1)The first methodinvolves controlling the clocks driving the SRL and D flip-flop.

• Initially after startup, the clock should be stopped.
• Once the EOS signal asserts from the STARTUP primitive, the clock can be restarted synchronously to the user's systemclock.
• The best way to control this is to use a BUFGCE, BUFR reset, or BUFHCE.
  • Do not use these elements for clocks providing feedback to the DCMs. Gating the feedback clock to the DCM might cause unreliable operation of the DCM.The only clocks that need to be controlled are the ones which go to the SRL and DFF elements in a design.

2) An alternative method uses theCE ports of individual synchronous elements which can be controlled instead of stopping the clock.

• Initially after startup, theCE ports should not be enabled.
• Once the EOS signal asserts from the STARTUP primitive, the CE pins can be enabled synchronously to the user's system clock.
• This solution cannot be used with inferred SRL logic.If working with inferred SRLs, use solution #1 instead.
• Be aware this technique may be more susceptible to timing and routing problems and should only be used if solution #1 can't be used

Both techniques can be used as appropriate.

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