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AR# 44177

LogiCORE IP 10-Gigabit Ethernet MAC v10.2 - "ConstraintSystem:58 - Constraint...sync_rx_reset_1_i/reset_out*" MAXDELAY = 4500 ps;...does not match any design objects


The LogiCORE IP 10-Gigabit Ethernet MAC v10.2 User Guide (UG148) provides reset path constraints. 

When I use those constraints in my design, I receive the following error message:

ConstraintSystem:58 - Constraint
<NET"*xgmac_core/BU2/U0/G_RX_RESET.G_SYNC_RESET_FALLING.sync_rx_reset_1_i/reset_out*" MAXDELAY = 4500 ps;>
NET"*xgmac_core/BU2/U0/G_RX_RESET.G_SYNC_RESET_FALLING.sync_rx_reset_1_i/reset_out*" does not match any design objects.


The reset path constraints provided in the LogiCORE IP 10-Gigabit Ethernet MAC v10.2 User Guide (UG148) are not valid. 

Please use the CORE Generator UCF constraints that are generated during the core generation process instead of the constraints provided in the user guide.

Revision History:
09/27/2011 - Initial Release

AR# 44177
Date 09/08/2014
Status Active
Type General Article
  • 10 Gigabit Ethernet Media Access Controller
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