We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 44193

Design Advisory for Spartan-6 FPGA Speed File - Updates for DCM Phase Alignment


The Spartan-6 FPGA speed files do not match the data sheet values for the DCM Phase Alignment. This issue is scheduled to be fixed in the ISE Design Suite 13.3 and later. A patch can be installed, found below, to run timing analysis for earlier software versions.


10/26/11 Update

The original patches that were provided with the readme dated 9/22/11 did not include the speed files for theautomotive (XA) or military (XQ) devices.All of the patches listed below are now updated and include these devices.You can confirm theupdated patch by the readme dated 10/26/11.


All Spartan-6 FPGA speed files are scheduled to be updated in ISE Design Suite 13.3 to correct errors in the DCM Phase Alignment values. The correct values have always been shown in the production specifications in the data sheet; these updates make the speed files match the data sheet. Designs that might be affected by the changes detailed below should be evaluated to confirm that they meet timing. Timing analysis can be run in ISE 13.3 software when it is available, or a speed file patch can be applied to run analysis on an earlier software version. To receive the patch, see the 'Workaround' section below.

The ISE 13.2 software speed file versions are v1.19 for the standard power devices and v1.07 for the lower power Spartan-6 -1L devices.The corrected speed files are v1.20 and v1.08, respectively.

Note that the lower power Spartan-6 -1L speed file is also being updated for the block RAM fMAX value (Xilinx Answer 44192).

DCM Phase Offset Change for All Speed Grades

The DCM phase offset between the CLKIN and CLKFB inputs, when CLK_FEEDBACK=1X, is being increased for all speed grades.The new values will match the values shown in the Spartan-6 Data Sheet (DS162); seeTable 54, CLKIN_CLKFB_PHASE (CLK_FEEDBACK=1X). This specification is referred to as Phase Error (PE) in the timing reports.

CLKIN_CLKFB_PHASE is being increased from 50 ps or 60 ps to 150 ps for all the standard power devices (-2, -2Q, -3, -3Q, -3N), and from 150 ps to 250 ps for the lower power -1L devices. Note that the data sheet specification is 100 ps higher when CLK_FEEDBACK=2X.However, the speed file does not differentiate between 1X and 2X feedback, so the value for CLK_FEEDBACK=1X is used. Customers using 2X feedback should account for the extra 100 ps in their timing analysis. A footnote is going to be added to the next revision of the Spartan-6 Data Sheet to note that the 2X feedback value must be manually accounted for in timing analysis.

Customers who have used the data sheet numbers for their timing analysis can continue to use the same numbers. Customers who have depended only on the speed file based timing analysis will see a slight reduction in their timing windows, and designs using DCM phase alignment should re-verify timing using the timing analyzer with the updated speed file, and designs using CLK_FEEDBACK=2X should add the additional 100 ps.


The following table summarizes the changes being made in the Spartan-6 speed files with respect to the DCM phase alignment values.



-3, -3Q
-3N -2, -2Q
ISE 13.2 and earlier
50 ps
60 ps
60 ps
150 ps
ISE 13.3
150 ps
250 ps


Verify designs to confirm that they meet these timing requirements. To use the updated values in timing analysis, either use ISE Design Suite13.3 or later software when it is available, or install the patch below for the specific software version needed.Please note, the patches below are the same as listed in (Xilinx Answer 44192), so one installation covers both items. Review the included Readme.txt for install instructions.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34856 Design Advisory Master Answer Record for Spartan-6 FPGA N/A N/A
46790 Spartan-6 FPGA Design Assistant - Troubleshooting Common Clocking Problems N/A N/A
AR# 44193
Date 01/25/2013
Status Active
Type Design Advisory
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2