This change will add an extra clock cycle to the startup state machine. This is a concern for customers who use a processor interface to configure their device and use a defined number of clocks, there are some potential issues where configuration does not complete to the stage where the EOS (end of startup) signal is released. The effects of DonePipe are explained in (Xilinx Answer 42128).
There has also been another change to Bitgen settings for 7 Series concerning DriveDone. This is described in (Xilinx Answer 44103).
** If DonePipe is disabled an external 330 ohm pullup resistor must be used to ensure DONE will transition high within one configuration clock cycle.