AR# 44237


13.3 - Bitgen - 7 Series - DonePipe option is now enabled by default


From ISE 13.3 design tools and forward, the BitGen option DonePipe will be enabled for all 7 series designs. This option adds a register to the DONE signal prior to being read by any configuration logic. A stronger internal pullup has also been added on DONE. These changes make the DONE transition more robust and not prone to issues with slow rise time that previous families experienced.


This change will add an extra clock cycle to the startup state machine. This is a concern for customers who use a processor interface to configure their device and use a defined number of clocks, there are some potential issues where configuration does not complete to the stage where the EOS (end of startup) signal is released. The effects of DonePipe are explained in (Xilinx Answer 42128).

There has also been another change to Bitgen settings for 7 Series concerning DriveDone. This is described in (Xilinx Answer 44103).

** If DonePipe is disabled an external 330 ohm pullup resistor must be used to ensure DONE will transition high within one configuration clock cycle.

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AR# 44237
Date 04/02/2013
Status Active
Type General Article
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