Description: Design contains a RAM16X1. The designer constraints several paths in the design with the following constraint.
There are five PAD to PAD paths. Four starting at each input PADs through the address pins on the RAM to the output PAD. The fifth path is from the input PAD through the WE pin on RAM to the output PAD.
When you run TRCE/Timing Analyzer each of these paths is reported and analyzed. If you add the following constraint.
The fifth path through the WE pin is no longer reported.
This is scheduled to be fixed in the next software release.