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AR# 44328

MIG Virtex-6 DDR2/DDR3 - Simulation Fails to Finish Calibration when SIM_BYPASS_INIT_CAL = "OFF"

Description

Simulation fails to finish calibration for DDR2/DDR3 when SIM_BYPASS_INIT_CAL = "OFF".

Solution

This is because when SIM_BYPASS_INIT_CAL = "OFF" in sim_tb_top, the read leveling algorithm does multiple iterations and applies the averaged results, which is impractical to run in simulation. This setting is intended for hardware implementations only.

To see the complete calibration sequence in simulation, except for the multiple read leveling iterations, set the following:

SIM_BYPASS_INIT_CAL = "OFF" in sim_tb_top
SIM_CAL_OPTION = "FAST_WIN_DETECT" in phy_top module

This will be included in the 13.4 Virtex-6 FPGA Memory Interface Solutions User Guide (UG406).

AR# 44328
Date Created 09/29/2011
Last Updated 02/14/2013
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG Virtex-6 and Spartan-6