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AR# 44329

MIG v3.9 Virtex-6 DDR3/DDR2 - AXI Designs are failing in ModelSim with a Segmentation Fault

Description

In some cases, the AXI interface designs are failing in simulation with segmentation fault errors due to an issue with ModelSim 6.6d.

Solution

This issue only affects MIG Virtex-6 DDR3 SDRAM and DDR2 SDRAM 72-bit and 144-bit designs. There is no workaround at this time until the issue is fixed by ModelSim.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
43130 MIG Virtex-6 and Spartan-6 v3.9 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43130 MIG Virtex-6 and Spartan-6 v3.9 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A
AR# 44329
Date Created 09/29/2011
Last Updated 05/22/2012
Status Archive
Type Known Issues
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG Virtex-6 and Spartan-6