Description

Solution

MIG 7 Series v1.3 asks the user to select a memory clock period that is derived from the chosen input clock frequency with the help of the Clocking Wizard. During this process, frequencies must be converted to periods (and vice versa) for MIG and the Clocking Wizard. In order to perform this conversion, a truncation mechanism is used for the system clock frequencies which results in a lower output period from PLL than the supported memory clock period. The out-of-range memory frequency then causes the component switching limit errors and simulation error messages.

Changing the input clock frequency to a value less than 350 MHz prevents this issue from occurring. This problem is scheduled to be fixed in the MIG 7 Series v1.4 (in ISE 13.4 software release).

Linked Answer Records

Master Answer Records

Associated Answer Records