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AR# 44372

13.3 XST - "ERROR:HDLCompiler:69 - "<*>.v" Line 24: <TESTONE> is not declared."

Description


13.3 XST Verific parser generates the following error message when a CASE statement present inside an ALWAYS block accesses a reg variable declared within a generate ... endgenerate block through its statements:

"ERROR:HDLCompiler:69 - "<*>.v" Line 24: <TESTONE> is not declared."

Solution


Take the following piece of code as an example:

module test2 #
(
parameter USE_TESTONE = 1
)
(
input wire Clk,
input wire select,
output reg testout
);

generate
if(USE_TESTONE == 1)
begin: TESTONE
reg testin;
end
endgenerate

generate
if(USE_TESTONE==1)
begin: TESTONEFUNC
always @ (posedge Clk)
begin
case(select)
0: testout <= TESTONE.testin;
1: testout <= TESTONE.testin;
endcase
end

end

endgenerate
endmodule

In the code above, testin is the reg variable declared within TESTONE generate ... engenerate block. This reg variable is assigned to testout inside the case ... endcase statement that is present inside an always block of the TESTONEFUNC generate ... endgenerate block. When the 13.3 XST Verific parser encounters this statement that is present within the case ... endcase statement, it generates the following error message due to the fact that it is not able to find the testin reg variable:

"ERROR:HDLCompiler:69 - "<*>.v" Line 24: <TESTONE> is not declared."

To work around this problem,
  1. create a wire signal
  2. assign the reg variable from the generate statement to this wire signal
  3. use this wire within the case...endcase statement

The same Verilog code is transformed as follows in order for XST to synthesize the code successfully:

module test2 #
(
parameter USE_TESTONE = 1
)
(
input wire Clk,
input wire select,
output reg testout
);

generate
if(USE_TESTONE == 1)
begin: TESTONE
reg testin;
end
endgenerate
wire tmp;
assign tmp = TESTONE.testin;
generate
if(USE_TESTONE==1)
begin: TESTONEFUNC
always @ (posedge Clk)
begin
case(select)
0: testout <= tmp;
1: testout <= tmp;
endcase
end
end
endgenerate
endmodule

In the code above, tmp is the wire that has been used to resolve this problem. By using this work-around, the XST Verific parser does not error out.

A CR has been filed against this issue.
AR# 44372
Date Created 12/09/2011
Last Updated 05/03/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 13.3