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AR# 44394

PlanAhead, 7 Series - What does margin in SSN analysis mean?


If I am targeting a 7 series FPGA in the PlanAhead tool and performing SSN, how is the tool analyzing the amount of noise in the system compared to the ideal margin?


Taking VDH (voltage drive high) Vih (voltage input high) this gives the logic 1 ideal margin. Vil (voltage input low) - VDL (voltage drive low) gives the logic 0 ideal margin. Using a hammer 101010 pattern at the resonant frequency, the noise at the far end of the line is measured for logic 1 and logic 0. The limit is the number of I/Os that can switch and still have remaining margin. The remaining margin is the minimum of logic 1 ideal margin logic1 noise and logic 0 ideal margin logic 0 noise.


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
31905 Simultaneously Switching Noise - Where can I find documentation on SSO/SSN? N/A N/A
AR# 44394
Date 12/15/2012
Status Active
Type General Article
  • PlanAhead
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