iMPACT 13.2 indirect SPI flash or BPI flash programming operations can fail on Kintex-7 devices when the following two conditions are met:
When the scenario above is met, iMPACT 13.2 loads the incorrect Kintex-7 FPGA indirect flash programming core that configures the I/O in banks 0, 14, and 15 with the 1.8V LVCMOS standard, instead of the 2.5/3.3V-compatible LVCMOS standard.
In some cases,it might appear that thecore file has not loaded with the following messages in the console (the core in fact is loaded but, is reported as not loaded incorrectly):
"INFO:iMPACT - Downloading C:\Xilinx\13.3\ISE_DS\ISE\data\cse\cseflash\kintex7\xc7k325t_xsdbbpi_lvcmos18 .cor core file.
INFO:iMPACT - Creating XC7K325T device.
PROGRESS_START - Starting Operation.
'2': Programming device...
Match_cycle = NoWait.
Match cycle: NoWait
LCK_cycle = NoWait.
LCK cycle: NoWait
INFO:Cse - Status register values:
INFO:Cse - 0011 1111 0101 1110 0000 1000 0100 0010
INFO:Cse - '2': Completed downloading bit file to device.
INFO:Cse - '2': Programming completed successfully.
PROGRESS_END - End Operation.
Elapsed time = 6 sec.
Core is not loaded."
How do I work around this issue and what is the risk for my device?
For the XC7K325T Initial ES devices, the incorrect core can cause potential I/O damage over an extended period.
The fix provided in the patch for this issue is to be included in the 13.3 ISE Design Suite release.
NOTE: This issue does not affect the KC705 development board asithas only the Kintex-7 device in the JTAG chain.