This happens because the integrated block throttles the transmit interface by deasserting trn_tdst_rdy_n. The AXI wrapper is not correctly anticipating this condition and if a packet is transmitted into the AXI wrapper from the user coincident with this stall, the packet will be dropped. This problem only happens if ASPM L0s entry is enabled on the endpoint.
ASPM L0s entry is enabled or disabled by the system. To know if the ASPM is enabled, read the Link Control register bits 1:0, which is located at address 0x68 in the core's configuration memory space. This information is also available on the user interface output port cfg_lcommand[1:0]. A setting of 00 means ASPM entry is disabled. See section 7.8.7 of the PCI Base Specification for more information on this register.
If the ASPM L0s entry is enabled or if it is unknown, then you must modify the AXI wrapper to allow the wrapper to recognize that the block will throttle the transmit interface when L0s is entered. This is done by modifying the top level source wrapper file, which is the same as the generated core's name. This file is found in the generated core's source directory and is either a Verilog or VHDL file.In this file,the parameter C_PM_PRIORITYmust be set to"True".
Aftermaking this modification, it is important to understand that the AXI transmit interface or the S_* interface can throttle the user in the middle of a packet by deasserting S_AXIS_TX_TREADY. This is in contrast to what the user guide says. Ensure that the design is modified to anticipate the deasssertion of S_AXIS_TX_TREADY during packet transfers.
Find the instantiation of the axi_basic_top module and modify the C_PM_PRIORITY parameter to be TRUE.
.C_DATA_WIDTH (32), // RX/TX interface data width
.C_FAMILY ("S6"), // Targeted FPGA family
.C_ROOT_PORT ("FALSE"), // PCIe block is in root port mode
.C_PM_PRIORITY ("TRUE") // Disable TX packet boundary thrtl
) axi_basic_top (
Find the instantiation of the axi_basic_top module and modify the C_PM_PRIORITY parameter. Do not modify the constant found near the top of the file as it is not used in the instantiation of the module.
axi_basic_top_inst : axi_basic_top
generic map (
C_DATA_WIDTH=> 32, -- RX/TX interface data width
C_FAMILY=> "S6", -- Targeted FPGA family
C_ROOT_PORT=> FALSE, -- PCIe block is in root port mode
C_PM_PRIORITY=> TRUE, -- Disable TX packet boundary thrtl
TCQ=> 1, -- Clock to Q time
C_REM_WIDTH=> 1, -- trem/rrem width
C_STRB_WIDTH=> 4 -- TSTRB width
01/18/2012 - Updated; added reference to 45072
10/07/2011 - Initial Release
Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.