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Functional simulation does not work on VCS (CR 576013) Description: VCS does not support the function call to calculate a localparam value used in the AXI4-Lite to IPIF bridge block. This function call has been reimplemented in a way that VCS will support.
AXI FIFO in example design can repeat the last word of data (CR617619) Description: If a frame has a full 64 bits valid in the final transfer of data for a frame, the data can be repeated and added as the first word in the next frame.
AXI TX FIFO in example design can get stuck FULL (CR605857) Description: The AXI FIFO waits for the end(tlast) of the frame to clear the FULL flag. If a flow control capable master is writing tready is de-asserted when full is asserted, then the master holds the data and tvalid and last is never asserted. This causes the TX FIFO to get stuck in FULL state forever.
In-band FCS and DIC cannot be enabled together on config vector (CR592405) Description: In-band FCS and DIC can be turned on at the same time when the AXI-Lite/IPIF interface is used, but when the configuration vector is used the Deficit Idle Count bit is inhibited.
TX/RX MTU size is unconstrained (CR 608810). Description: Although only values of 1518 or greater are legal for TX and RX MTU size, the core will not enforce this size on write. Please ensure only legal values are written to the MTU register for correct core operation.
(Xilinx Answer 45081) LogiCORE IP 10-Gigabit Ethernet MAC v11.2 (AXI) - Core Returns Incorrect Version Number