For installation instructions for this release, please go to:
For system requirements:
This file contains release notes for the Xilinx LogiCORE IP Virtex-6 FPGA GTX Transceiver Wizard v1.11 solution.
For the latest core updates, see the product page at:
The following device families are supported by the core for this release.
-CR 609585 - Implemented AR # 39430 (Clocking Use models for Buffer bypass)
The most recent information, including known issues, workarounds, and resolutions for this version is provided in the IP Release Notes Guide.
To obtain technical support, create a WebCase at www.xilinx.com/support. Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.
Core Release History
Date By Version Description
10/26/2011 Xilinx, Inc 1.11 ISE 13.3 support
06/22/2011 Xilinx, Inc 1.10 ISE 13.2 support
03/01/2011 Xilinx, Inc 1.9 ISE 13.1 support
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
04/24/2009 Xilinx, Inc. 1.1 ISE 11.1 support