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AR# 44541

Soft Error Mitigation Controller - Release Notes and Known Issues for v1.1 to v3.4

Description

This Release Notes and Known Issues Answer Record is for the Soft Error Mitigation Controller, first released in ISE Design Suite 12.3 for all ISE versions up to 14.4, and all Vivado tool versions up to 2012.4.

Solution

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide.

For Known Issues for SEM v4.0 and later for Vivado, see (Xilinx Answer 54642).
For Known Issues for SEM v3.5 and later for ISE only, see (Xilinx Answer 54733)

For design tips and knowledge, please reference Soft Error Mitigation Controller - Frequently Asked Questions (Xilinx Answer 42103)

New Features for v3.4

  • ISE
    • ISE 14.4 design tools support

Supported Devices for v3.4

The following device families are supported by the core for this release.

  • ISE Design Suite
    • All Artix-7 devices
    • All Zynq devices
    • All Virtex-7 devices (excluding SSI)
    • All Kintex-7 devices
    • All Virtex-6 devices
    • All Spartan-6 devices
  • Vivado
    • All Artix-7 devices
      All Virtex-7 devices
    • All Kintex-7 devices

Note: For the previous version "New Features" and "Supported Devices", see the readme.txt or version information file available with the generated core.

Known Issues

This table correlates the core version to the first software release version in which it was included.

Core Version
ISE Version
Vivado Version
v3.6 ISE 14.6 -
v3.5 ISE 14.5 -
v3.4 ISE 14.4 2012.4
v3.3 ISE 14.2 2012.2
v3.2
ISE 14.1
2012.1
v3.1
ISE 13.3
v2.1
ISE 13.2
v1.3
ISE 13.1
v1.2
ISE 12.4
v1.1
ISE 12.3

Note: The "Version Found" column lists the version in which the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record
Title
Version Found
Version Resolved
(Xilinx Answer 65554) Soft Error Mitigation  PG036 Section Update: Sample Spartan-6 Reliability Estimation for S6 SEM v3.4 and newer v3.4 N/A
(Xilinx Answer 65308) SEMIP - 7 series and Zynq-7000 Enhanced Repair initialization times are incorrect in PG036 for select devices. PG036 will be updated with the correct numbers in Vivado 2015.3 v3.4

PG036 ISE v3.4.1

PG036 Vivado 2015.3

(Xilinx Answer 65402) Soft Error Mitigation (SEM) IP - When performing error injection into configuration memory high performance interfaces may experience bit errors v3.4 N/A
(Xilinx Answer 55276) Soft Error Mitigation v3.4 - Spartan-6 LXT Scan Addressing is incorrect and will cause a false alarm v3.4 v3.5
(Xilinx Answer 47292) Example Design UCF Pinout Constraints for the VC707 and KC705 Boards N/A N/A
(Xilinx Answer 47291) Example Design XDC Pinout Constraints for the VC707 and KC705 Boards N/A N/A
(Xilinx Answer 53445) Vivado 2012.4 produces CRITICAL WARNINGs which can be ignored v3.4 v4.0 (Vivado)
(Xilinx answer 53438) v3.4 - Updated EXT shim module for use with 512 Mb and 1 Gb SPI Flash * v3.4
(Xilinx Answer 52716) Design Advisory for Spartan-6 FPGAs - Configuration Readback including SEM_IP or POST_CRC causes power distribution network noise affecting SelectIO and GTP interfaces All v3.4
(Xilinx Answer 51043) SEM IP Core failure to initialize when programmed through a Digilent Programming Solution v3.2 Not Resolved
(Xilinx Answer 52277) Vivado 2012.3 produces CRITICAL WARNINGs which can be ignored v3.3 v3.4
(Xilinx Answer 50962) The XDC set_max_delay constraints are incorrect v3.2 v3.3
(Xilinx Answer 50778) SEM IP Targeting the XC7VC550T or XCK420T Devices Must Update to Version 3.3 v3.2 v3.3
(Xilinx Answer 47402) Vivado 2012.1 / ISE Design Suite 7 Series maximum frequency is 70 MHz
v3.2
v3.5 and v4.0
(Xilinx Answer 47401) ISE Design Suite - Timing Error (Setup Violation) on Virtex-7 980T devices
v3.2
v3.3
(Xilinx Answer 47400) Vivado 2012.1 - Period constraint rounding to nearest nano-second
v3.2
v3.3
(Xilinx Answer 47338) Vivado 2012.2 - Place Error when using pblock constraints on Virtex-7 and Kintex-7
v3.2
Not Resolved
(Xilinx Answer 47202) Vivado 2012.1 - How to generate core and example design in Vivado 2012.1
v3.2
N/A
(Xilinx Answer 47295) Vivado 2012.1 - No Testbench Generated even though option box checked
v3.2
v3.2
(Xilinx Answer 44545) ERROR:Bitgen:342 - This design contains pins which are not constrained...
v3.1
N/A
(Xilinx Answer 44546) EXT Shim module generates the use 32-bit addressing command for all 7 Series configurations
v3.1
v3.2
(Xilinx Answer 42483) Spartan-6 Soft Error Mitigation Controller - Component switching limit errors
v2.1
N/A
(Xilinx Answer 42482) Hold time violations in par and trce when targeting Virtex-6 LX760 -1L
v2.1
v3.3
(Xilinx Answer 39350) Timing Simulation Error: Warning: /X_FF RECOVERY Low VIOLATION ON RST WITH RESPECT TO CLK
v1.1
N/A
(Xilinx Answer 46112) Essential Bits not including SR/CRUSEDMUX associated bits using ISE version prior to 13.4
*
ISE 13.4
(Xilinx Answer 44544) Soft Error Mitigation Controller - Resolved Issues in v3.1
v3.1
v3.1
(Xilinx Answer 42997) Mistake in User Guide regarding address pointers to replacement and classification data
v2.1
v3.1
(Xilinx Answer 40991) Correction by Replace not supported with EasyPath Devices
v2.1
v3.1
(Xilinx Answer 42494) Correction by Replace and Classification features are not supported in Spartan-6
v2.1
v3.1
(Xilinx Answer 43106) External Shim interfacing with SPI device issues the "enable 32-bit addressing" multiple times at startup
v2.1
v3.1
(Xilinx Answer 37935) After Meeting Timing, PAR Reports Hold Violation Upon Running Another Routing Phase
v1.1
v2.1
(Xilinx Answer 38130) Virtex-6 -1L Speed Grade ICAP Frequency Limited to 60 MHz
v1.1
v1.2


Revision History


06/03/2013 Updated for ISE 14.6, made this solution explicit for old versions, for newer 54642,54733 is available
04/03/2013 Updated for ISE 14.5
01/15/2013 Updated table with Answer Records 47292 and 47291
12/18/2012 Updated for ISE 14.4 and Vivado 2012.4
10/25/2012 Updated for ISE 14.3 and Vivado 2012.3
07/25/2012 Updated for ISE 14.2 and Vivado 2012.2
05/08/2012 Updated for ISE 14.1 and Vivado 2012.1
02/01/2012 Added 46112
10/26/2011 Initial Release; v3.1; ISE 13.3
AR# 44541
Date Created 10/13/2011
Last Updated 10/21/2015
Status Active
Type Release Notes
Devices
  • Spartan-6
  • Virtex-6
  • Virtex-7
  • More
  • Kintex-7
  • Artix-7
  • Zynq-7000
  • Less
Tools
  • ISE
  • Vivado Design Suite - 2012.4
  • Vivado Design Suite - 2012.3
  • More
  • Vivado Design Suite - 2012.2
  • Vivado Design Suite - 2012.1
  • Less
IP
  • Soft Error Mitigation