When running bitgen using the Soft Error Mitigation Controller, a DRC error might occur:
"ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to specific location or have an undefined I/O Standard (IOSTANDARD)..."
For all Soft Error Mitigation Controller known issues, see (Xilinx Answer 44541).
The UCF provided for the example design targeting 7 Series devices does not have LOC constraints, although, it does contain IOSTANDARD constraints.To evaluate the example design in hardware, you must add appropriate LOC constraints. Further, the IOSTANDARD constraints must be reviewed and adjusted, if necessary, based on the LOC constraints and the I/O bank voltages in use.
The implementation scripts targeting 7 Series devices have bitgen and any dependent steps commented out. After making modifications to the UCF, the script should be modified to enable these steps.
See (Xilinx Answer 41615) for more information regarding this error.
10/26/2011 - Initial Release