Description

The quality of the reference clock supplied to the PLL in the 7 SeriesFPGA Transceivers can greatly impact the performance of the transmit jitter and receive jitter tolerance. Jitter or phase noise from the reference clock plays an important role in determining this performance--phase noise being the preferred specification method as it allows the designer to incorporate the various frequency components that a time-based jitter specification might overlook.

This Answer Record contains the reference clock phase noise limits that Xilinx recommends based on the PLL settings being used.

Solution

Depending on the reference clock being used, a different mask needs to be applied. The tables below describe the points of a mask above which the reference clock phase noise should not exceed. If a reference clock does exceed these masks, it results in additional jitter on TX data.

For 7 series GTX and GTH transceivers, the following tables provide the phase noise masks for QPLL and CPLL. For 7 series GTP transceivers,theCPLL table providesthe phase noise mask.

QPLL:

Note: If your desired reference clock rate is not listed in the table above, please use the phase noise mask for the nearest reference clock frequency.

CPLL:

Note: If your desired reference clock rate is not listed in the table above, please use the phase noise mask for the nearest reference clock frequency.

Linked Answer Records

Associated Answer Records