I am implementing the example timing of the control signals as specified in the AXI VDMA datasheet (register direct mode).
The core appears to handle up to one or two lines of data without issue, but after that, I lose my tready signal and it never comes back up except on reset.
The core can lock up like this if the DMAIntErr flag fires in one of the DMASR registers.
As per page 76 of the datasheet, this error can occur under one of two conditions:
You should also check the following: