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AR# 44572

AXI VDMA - This core is locking up after a few packets of data, what can I do to debug this?


I am implementing the example timing of the control signals as specified in the AXI VDMA datasheet (register direct mode).

The core appears to handle up to one or two lines of data without issue, but after that, I lose my tready signal and it never comes back up except on reset.


The core can lock up like this if the DMAIntErr flag fires in one of the DMASR registers.

As per page 76 of the datasheet, this error can occur under one of two conditions:

  1. The HSIZE or VSIZE registers are zero at the time VSIZE is written.
    • Check the register values during configuration of the core to make sure that the correct HSIZE/VSIZE is being written to the correct address in the register space.
      (Note: HSIZE is specified in BYTES, but VSIZE is specified in number of lines)
    • Make sure the VSIZE register is written last.
  2. The packet size is not correct as per the values specified in HSIZE.
    • Make sure that the packet size is correct with respect to HSIZE (check for off-by-one errors)


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AR# 44572
Date 10/03/2014
Status Active
Type General Article
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