At the end of configuration, when the FPGA transitions from Configuration Mode to User Mode, all of the multi-purpose I/Os transition from the default (power-on setting) IOSTANDARD to the user-defined IOSTANDARD during the STARTUP sequence.
As the FPGA switches from Configuration Mode to User Mode, if the multi-purpose I/O bank_14 voltage is undefined in the user design, the EMCCLK is effectively turned OFF in the middle of the STARTUP sequence, and the STARTUP sequence stops at GTS.
How do I work around this issue?
EMCCLK is included in bank 14, which has many dual purpose pins used for configuration. The bank_14 voltage needs to be defined for EMCCLK usage to be supported.
The EMCCLK pin is enabled with the following write_bitstream property:
When setting this property, a command is inserted into the bitstream that switches the configuration clock source from the internal oscillator to EMCCLK.
To ensure that the EMCCLK input path remains enabled through the startup transition as the configuration clock source, at least one of the following implementations must be used: