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AR# 44637

LogiCORE IP JESD204 v1.1 - How can I change CPLLLOCKDETCLK in the example design to have a free running independent clock as an input?

Description


In the 7 Series FPGAs GTX Transceivers User Guide (UG476), Table 2-9 indicates that QPLL and CPLLLOCKDETCLK_IN should be a free running clock independent to reference clock or the clock derived from reference clock.

However, in example designs this clock is just TXUSRCLK2 for TX and RXUSRCLK2 for RX, which leads to wrong PLL function/status in some conditions.

For the LogiCORE IP JESD204 v1.1, how can I change CPLLLOCKDETCLK in the example design to have a free running independent clock as an input?

Solution


In the example design provided with the core, the DRP clock is generated from the same clock as the transceiver usrclk which is invalid. The DRP clock must be independent of the usrclk and less than 125 MHz in a -1, or 150 MHz in a -2 or -3.

In <corename>_block.v change:
.DRP_CLK_IN (core_clk),

to:
.DRP_CLK_IN (s_axi_aclk),

Note that if the s_axi_aclk operates faster than the DRP clock specification of 125 MHz in a -1 or 150 MHz in a -2 or -3, then an alternative clock should be used. Also, the s_axi_aclk should not be derived from the GTX output clock (including core_clk).

For LogiCORE IP JESD204 Release Notes from other versions, see (Xilinx Answer 44405).
AR# 44637
Date Created 10/19/2011
Last Updated 11/21/2011
Status Active
Type Known Issues
IP
  • JESD204