Version Found: 1.00.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)
The AXI Bridge for PCI Express Core does not have a Design Rules Check (DRC) when the Base Address Register (BAR) range overruns the AXI memory space.
For example, the following condition should issue a DRC error:
(Please assume unsigned arithmetic)
C_PCIEBAR2AXIBAR_# + 2^ C_PCIBAR_LEN_# > 0xFFFF_FFFF
Note: The "Version Found" columnists the version that the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
If the condition above is met, memory writes will not reach the expected AXI locations and might write to other valid areas of the memory mapped space.
Memory reads will either result in Completion TLPs with Unsupported Request, or with data from other valid areas of the memory mapped space.