Version Found: v1.1
Version Resolved and other Known Issues: see (Xilinx Answer 40469).
Is synthesis with Synplify supported?
Synthesis with Synplify is not officially supported as of the v1.3 release in ISE Design Suite 13.4. This is because no testing has been done to verify that the core functions properly when the wrapper is synthesized with Synplify. Support for Synplify is planned for a future release.
If Synplify is selected as the flow in the CORE Generator tool, scripts are generated for Synplify. These are provided as reference for users who want to use Synplify even though it is not an officially supported flow.
One of these scripts, the implement.bat[sh] file, calls Synplify twice. Although it causes no functional problem, the only part needed is:
#Synthesize the Example Design Files
echo 'Synthesizing example design with Synplify';
Synplify_pro -batch synplify.prj
cp Synplify/xilinx_pci_exp_ep.edf ./results/xilinx_pcie_2_1_ep_7x.edf
echo 'Running ngdbuild'
Update for 7 Series Integrated Block for PCI Express v1.6 - Verilog version is now officially supported. However, VHDL is not supported yet.
07/25/2012 - Updated for v1.6 Release
03/06/2012 - Updated message on Synplify support.
12/06/2011 - Added version resolved reference to Answer Record 40469
10/27/2011 - Initial release
NOTE: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.