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AR# 44732

7 Series Integrated Block for PCI Express - ISIM example script fails to compile when using VHDL

Description


Version Found: v1.2
Version Resolved and other Known Issues: See (Xilinx Answer 40469).

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

The 7 Series Integrated Block Wrapper v1.2 for PCI Express core includes an ISIM simulation script to simulate the PIO example design. If the VHDL version of the core is generated, the ISIM script will fail during compilation. The following error will be reported:

"ERROR:HDLCompiler:837 - "../../source/pcie_7x_v1_2_pipe_clock.v" Line 224: Type boolean does not match with a string literal
ERROR:HDLCompiler:839 - "../../source/pcie_7x_v1_2_pipe_clock.v" Line 224: Type real does not match with the integer literal
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit board in library work failed"

Solution


This is a known issue with the 7 Series Integrated Block Wrapper for PCI Express v1.2 core.

To work around this issue, open the simulate_isim.bat or simulate_isim.sh with a text editor. The simulate_isim.bat is used for Windows and the simulate_isim.sh is used for Linux. The ISIM script needs to compile the glbl.v file first because this simulation uses both VHDL and Verilog.

Add the following line for Windows (simulate_isim.bat):
vlogcomp -work work %XILINX%/verilog/src/glbl.v

For Linux, add the following line:
vlogcomp -work work $XILINX/verilog/src/glbl.v

This command needs to be added before the fuse command.

Next, the fuse command needs to have two changes made; the glbl needs to be referenced and also the Verilog Unisim library needs to be correctly spelled as shown below:

fuse work.board work.glbl -L unisims_ver -L unimacro_ver -L unisim -L unimacro -L secureip -o demo_tb

The ISIM script is now complete. However, there is also an issue with ISIM that the user must work around.

The following 9 ports of the pcie_7x_v1_2_pipe_wrapper are tied to (others => '0') in the pcie_7x_v1_2_gt_top module:

PIPE_TXEQ_CONTROL
PIPE_TXEQ_PRESET
PIPE_TXEQ_PRESET_DEFAULT
PIPE_RXEQ_CONTROL
PIPE_RXEQ_PRESET
PIPE_RXEQ_LFFS
PIPE_RXSLIDE
PIPE_RXEQ_TXPRESET

These signals need to be tied to a bus tied to zero with a width matching each port's width. After this change, run the script and the simulation should work properly.

Revision History

12/06/2011 - Added version resolved reference to Answer Record 40469
10/26/2011 - Initial Release
AR# 44732
Date Created 10/26/2011
Last Updated 12/06/2011
Status Active
Type Known Issues
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )