NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
The 7 Series Integrated Block Wrapper v1.2 for PCI Express core includes an ISIM simulation script to simulate the PIO example design. If the VHDL version of the core is generated, the ISIM script will fail during compilation. The following error will be reported:
"ERROR:HDLCompiler:837 - "../../source/pcie_7x_v1_2_pipe_clock.v" Line 224: Type boolean does not match with a string literal ERROR:HDLCompiler:839 - "../../source/pcie_7x_v1_2_pipe_clock.v" Line 224: Type real does not match with the integer literal ERROR:Simulator:777 - Static elaboration of top level VHDL design unit board in library work failed"
This is a known issue with the 7 Series Integrated Block Wrapper for PCI Express v1.2 core.
To work around this issue, open the simulate_isim.bat or simulate_isim.sh with a text editor. The simulate_isim.bat is used for Windows and the simulate_isim.sh is used for Linux. The ISIM script needs to compile the glbl.v file first because this simulation uses both VHDL and Verilog.
Add the following line for Windows (simulate_isim.bat): vlogcomp -work work %XILINX%/verilog/src/glbl.v
For Linux, add the following line: vlogcomp -work work $XILINX/verilog/src/glbl.v
This command needs to be added before the fuse command.
Next, the fuse command needs to have two changes made; the glbl needs to be referenced and also the Verilog Unisim library needs to be correctly spelled as shown below: