My design is failing with the following error:
The Slice component that is mentioned in the error message multiple times contains LUTs that have three different BUFR nets as inputs.
The three BUFRs are LOC'd to three consecutive clock regions.
Although the clock placer was unable to find a solution, the slice component can be legally placed in the middle clock region of the three.
As this is a low frequency use case, this will remain a limitation in ISE Design Suite.
In the meantime, the work around is to override the error with the XIL_PAR_DEBUG_IOCLKPLACER variable.
For general information about setting ISE environment variables, see (Xilinx Answer 11630).