UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 44820

Virtex-6 FPGA MMCM CLOCK_HOLD Behavior

Description

The Virtex-6 FPGA Mixed-Mode Clock Manager (MMCM) provides an attribute named CLOCK_HOLD. When this attribute is set to true and when the input clock is lost, it serves to maintain the VCO frequency close to the frequency prior to losing the input clock.

When the input clock returns, the MMCM re-acquires the lock again without the need for a reset of the MMCM. The documentation does not specify the output clock behavior when the input clock is lost while the CLOCK_HOLD attribute is set to TRUE.

  • What is the VCO frequency during this time?
  • Is the output a usable clock?

Solution

With the CLOCK_HOLD attribute set to TRUE for the MMCM and when the input clock is lost, the LOCKED output of the MMCM drops low. Whenever the LOCKED output of the MMCM drops low, you do not want to use the output clocks in the design. This is because the output clocks are not usable in this state and you should avoid using the outputs even with the CLOCK_HOLD attribute set to TRUE. Whenever the input clock to the MMCM stops, LOCKED will drop low.

The main reason to use the CLOCK_HOLD attribute is to allow the MMCM to achieve the lock again after the input clock has been lost without the need for a reset. This attribute is not intended to be used for the MMCM output clocks when an input clock is not present.

AR# 44820
Date Created 11/04/2011
Last Updated 05/23/2013
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-6QL
  • Less