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AR# 4483

FPGA Express: How to instantiate OSC4 in HDL (XC4000E/EX/XL, Spartan/XL)

Description

Keywords: VHDL, Verilog, instantiate, OSC, oscillator, internal clock
generator, FPGA Express, XC4000E/EX/XL/XV, Spartan/XL

Urgency: Standard

General Description:
How to instantiate OSC4 (Internal 5-Frequency Clock-Signal Generator) in HDL

Solution

1

--For VHDL
--library declarations
library IEEE;
use IEEE.std_logic_1164.all;

--entity declaration
entity osc4ex is
port(din:in std_logic;
dout:out std_logic);
end osc4ex;


--architecture declaration
architecture xilinx of osc4ex is

--signal declaration
signal to_bufg:std_logic;
signal clk:std_logic;

--component declarations
component OSC4
port (F8M: out std_logic;
F500K: out std_logic;
F16K: out std_logic;
F490: out std_logic;
F15: out std_logic);
end component;

component BUFG
port (I: in std_logic;
O: out std_logic);
end component;

begin

--component instantiations
oscut: OSC4 port map (F8M=>open, F500K=>to_bufg, F16K=>open, F490=>open,
F15=>open);
bufut: BUFG port map (I=>to_bufg, O=>clk);

--sequential logic
process(clk)
begin
if clk'event and clk='1' then
dout<=din;
end if;
end process;

end xilinx;

2

//For Verilog
//module declaration
module osc4ex (din, dout);

input din;
output dout;

//signal declaration
reg dout;
wire to_bufg;
wire clk;

//component instantiation
OSC4 oscut (.F8M(), .F500K(to_bufg), .F16K(), .F490(), .F15() );
BUFG bufut (.I(to_bufg), .O(clk));

//sequential logic
always @ (posedge clk)
begin
dout=din;
end

endmodule
AR# 4483
Date Created 08/31/2007
Last Updated 10/05/2008
Status Archive
Type General Article