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AR# 44830: 13.3 Place - Spartan-3 Series - "ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair"
13.3 Place - Spartan-3 Series - "ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair"
In a design targeting Spartan-3 Series FPGAs, the following error occurs during PAR.
How can I resolve it?
ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair. The clock component<u_gsk_dcm/DCM_SP_INST> is placed at site<DCM_X0Y0>. The clock IO/DCM site can be paired if they are placed/locked in the same quadrant. The IO component<CLKIN_IN> is placed at site<P57>. This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. < NET "CLKIN_IN" CLOCK_DEDICATED_ROUTE = FALSE;> < PIN "u_gsk_dcm/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;>
This error occurs when the GCLK/DCM site pair are not placed in the same quadrant.
In Spartan-3 series FPGAs, DCM only has fast dedicated routing when the GCLK sites are in the same quadrant.
For detailed information, please refer to the "Spartan-3 Generation FPGA User Guide".
To resolve this error, check the following:
Is there a DCM site available for the GCLK to use dedicated routing? If not, try changing the clock input pad to the other quadrants which have a DCM available.
If the clock input pad cannot be changed on the PCB, set the CLOCK_DEDICATED_ROUTE constraint mentioned in the error message in UCF to allow non-dedicated routing. Be aware that non-dedicated routing leads to long delay on the clock path and the delay from the clock input pad to the DCM cannot be compensated for by the DCM. The timing performance can suffer as a result. Check your timing report to see if your timing requirements are met.