Errors similar to the following occur when elaborating the design in the PlanAhead tool:
These critical warnings do not cause any issue when the design is implemented, so they can be safely ignored.
However, there is a similar warning message to that mentioned in (Xilinx Answer 43315)
The issue described there has been fixed in the PlanAhead 13.4 software, but in earlier versions it did result in constraints being ignored.
You should review the pad report to verify that the ports are correctly placed.
The issue outlined in the Article Description above is visual only and does not affect the implementation of the design.
As a result it will not to be fixed in the current ISE software.
However, it is scheduled to be fixed in the next generation of Xilinx software.