UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 44937

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.1 - Changes required to implement the core on 7-Series Initial ES silicon

Description

To successfully implementLogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.1 on 7 Series Initial ES silicon, some changes are required. The 7 Series FPGAs Transceivers Wizard should be updated to v1.5rev1, updated reset logic is needed and updated clocking logic might be needed. Please apply all the changes listed below before testing it on the hardware.

Solution

Replace the GTX wrapper files with GTX Wizard v1.5rev1(from ISE13.4) for latest Initial ES GTX attributes

1) Run 7 Series Gigabit Transceiver Wizard v1.5rev1.(To get the Initial ES silicon drop down be sure to select a part and package that supports Initial ES silicon in the 7 Series Gigabit Transceiver Wizard, see (Xilinx Answer 43244) for more details.)

a) If using 1000BASE-X or SGMII without the fabric elastic buffer (on page 3 of the GUI, select under SGMII Capabilities "10/100/1000 Mb/s (restricted tolerance for clocks) or 100/1000 Mb/s"):
i. Set name as "GTWIZARD".
ii. Select "Initial ES" Silicon Version.
iii. Select "gigabit ethernet" in the protocol template.
b) If using SGMII with the fabric elastic buffer (on page 3 of the GUI, select under SGMII Capabilities "10/100/1000 Mb/s (clock tolerance compliant with ethernet specification)).
i. Set name as "GTWIZARD".
ii. Select "Initial ES" Silicon Version.
iii. Select "gigabit ethernet" protocol template.
iv. On page 2, for RXUSERCLK source select RXOUTCLK
v. On page 3, under RX COMMA detection, select Two Byte Boundaries.
vi. On page 4, under Clock Correction, deselect Use Clock Correction.
2) Copy the generated gtwizard.v(hd) and gtwizard_gt.v(hd) fileinto the example_design/transceiver folder.
3) In the gtwizard.vhd/vand gtwizard_gt.vhd/v file:
a)Comment out these ports on GTWIZARD:
i.GT0_RXBYTEISALIGNED_OUT
ii. GT0_RXBYTEREALIGN_OUT
iii. GT0_RXCOMMADET_OUT
iv. GT0_RXPCSRESET_IN
v. GT0_TXPCSRESET_IN
b)Comment out these ports on GTWIZARD_GT:
i.RXBYTEISALIGNED_OUT
ii.RXBYTEREALIGN_OUT
iii. RXCOMMADET_OUT
iv. RXPCSRESET_IN
v. TXPCSRESET_IN
c) Keep the following ports open on GTXE2_CHANNEL:
i. RXBYTEISALIGNED
ii. RXBYTEREALIGN
iii. RXCOMMADET
d) Map these signals to ground on GTXE2_CHANNEL:
i. RXPCSRESET
ii. TXPCSRESET
4) If not using SGMII with the fabric buffer in transceiver.v/vhd file,comment out the GTWIZARD port: GT0_RXOUTCLK_OUT

Update Wrappers to drive MMCM locked to the transceiver netlist:

1)Add an input port to core_name_block and transceiver called mmcm_locked.
2)In the core_name_example_design.v/vhd file:
a) create signal mmcm_locked
b) connect signal mmcm_locked to LOCKED port of MMCM used to generate userclk and userclk2 and to the mmcm_locked input added to the core_name_block
3) In the transceiver.v/vhd file, drive GT0_TXUSERRDY_IN and GT0_RXUSERRDY_IN with mmcm_locked. (TXUSERCLK/RXUSERCLK was previously driven by cplllock)
4) In core_name_block.v/vhd map mmcm_locked to the DCM_LOCKED input port on the core netlist

Reset Requirements Upon Configuration (Xilinx Answer 43482) (These changes have been implemented in v11.2 and later of the Ethernet 1000BASE-X PCS/PMA or SGMII core.)

1) In the example design:
a.mask clock generation from MMCM by keeping the MMCM in reset (mmcm_reset) till the transceiver is reset.
b.pass the independent_clock_bufg to transceiver.
2) In the block module
a. Pass independent_clock_bufg to transceiver
3) In the transceiver.vfile:
a. Added wait logic after global reset is received (pmareset)
b. Logic for generation of reset for GT (reset_pulse)
c. Resetdone signal to keep MMCM under reset.

Implement the TXOUTCLK and RXOUTCLK Ports Restrictions (Xilinx Answer 43244).

1) If using 1000BASE-X or SGMII without the fabric elastic buffer (on page 3 of the GUI, select under SGMII Capabilities "10/100/1000 Mb/s (restricted tolerance for clocks) or 100/1000 Mb/s"), no changes are needed.
2) If using SGMII with the fabric elastic buffer (on page 3 of the GUI, select under SGMII Capabilities "10/100/1000 Mb/s (clock tolerance compliant with ethernet specification)).

The core uses TXOUTCLK for TX side and RXOUTCLK for RX side. So that both clocks are not used, IBUFDS_GTXE2 can be used to instead of TXOUTCLK.

Implement known Transceiver Software Use Model Changes (Xilinx Answer 43339) if required.

Revision History
02/23/2012 - Updated to have MMCM locked drive RX/TXUSRRDY instead of RX/TXPCSRESET
02/21/2012 - Updated to provide specific details on changes needed, and added update to use MMCM_LOCKED for reset logic.
11/09/2011 - Initial Release

AR# 44937
Date Created 02/21/2012
Last Updated 05/19/2012
Status Active
Type Known Issues
IP
  • Ethernet 1000BASE-X PCS/PMA or SGMII