AR# 44946

LogiCORE IP JESD204 v1.1 - Why do I not see the example design files when the core is generated?


For the LogiCORE IP JESD204 v1.1, when I generate a JESD204B core in 13.3, I do not see any example files generated. Why?


Currently, you can only see example files when the language is set to Verilog.

ForLogiCORE IP JESD204 Release Notes from other versions, see(Xilinx Answer 44405).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44405 LogiCORE IP JESD204 - Release Notes and Known Issues N/A N/A
AR# 44946
Date 12/15/2012
Status Active
Type General Article