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AR# 44972

AXI Bridge for PCI Express FAQ

Description

This answer record provides answers to frequently asked questions. Please refer to the table below.

Solution

Article Number
Article Title
(Xilinx Answer 47603)
Converting the BSB Endpoint into a Root Complex
(Xilinx Answer 43371)
Working Example Design for the ML605 Development Board
(Xilinx Answer 43677)
Working Example Design for the SP605 Development Board
(Xilinx Answer 43706)
How to connect the axi_aclk and the axi_ctl_aclk ports
(Xilinx Answer 44111)
How to adjust the transceiver settings
(Xilinx Answer 44929)
Reading from the Control Registers in the Bridge Returns Incorrect Values
(Xilinx Answer 45061)
Instance names of transceivers for location constraints
(Xilinx Answer 45158)
Does the bridge need to be setup via the control interface?
(Xilinx Answer 45159)
Is a processor necessary for the bridge?

Revision History:
04/29/2012 - Added 47603
11/27/2011 - Added 45158and45159
11/10/2011 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A

Child Answer Records

AR# 44972
Date Created 11/30/2011
Last Updated 02/20/2013
Status Active
Type General Article
IP
  • AXI PCI Express (PCIe)