AR# 45011

Description

**The fix for this issue is in the ISE 13.4 software, which is now available on www.xilinx.com/download**

The BUFPLL LOCK output in Bank 2 of all Spartan-6 devices does not function properly using ISE 13.3 and earlier software.

Solution

In ISE 13.4 and later software, the BUFPLL LOCK output behaves as expected in all banks. InISE 13.3 and earliersoftware, in all Spartan-6 devices, a modeling was identified for BUFPLLs in Bank 2 (BUFPLL_X1Y0, BUFPLL_X1Y1). As a result, the BUFPLL LOCK output has beenconnected High. Because the LOCK output is used only as a status signal, the BUFPLL and any IOLOGIC connected within Bank 2 will operate correctly. In the event that the PLL is reset, the BUFPLL output signals will be reset as well, consistent with normal BUFPLL operation, although LOCK will stay high throughout.

The BUFPLL LOCK output serves the exact same function as the PLL LOCKED signal except that it does not go high until the PLL has locked and the BUFPLL has aligned the SERDESSTROBE signal correctly. Because a user could be using the LOCK output to control the start of operation, designs may start before the BUFPLL or potentially the PLL has correctly locked. Designs using XAPP1064 in Bank 2 should be modified. MIG/MCB designs will not be affected.

The following show the LOCK behavior of the BUFPLL in Bank 2:

Next Steps:

• Identify if a BUFPLL inBank 2 is used. This can be done in FPGA Editor or PlanAhead tool bylocating BUFPLL_X1Y0 andBUFPLL_X1Y1 and ascertaining whether they have been used in the design. It can also be done by looking at the Timing Report and searching for BUFPLL_X1Y0 and BUFPLL_X1Y1 to see if they are used.
• The effect of this issue on a design depends on how the LOCK signal is used in the design. If one or both of the BUFPLLs in Bank 2 are used, determine the application risk of LOCK always being high. Here are a two examples ofitems to check:
  • Is the LOCK signal used to enable/reset downstream logic such as IOSERDES?
  • If the PLL output clock is lost but the BUFPLL LOCK signal is still high, could that have a negative effect on the design?
• If the LOCK signal is required in the design, see below for a possible alternative.

Alternatives/Workarounds:

• Use ISE 13.4 software, which is now available.Re-implement the design with that version.

If ISE 13.4 cannot be used, some other options include:

• Move the PLL/BUFPLL to a bank other than Bank 2.
• Emulate the BUFPLL LOCK output by registering the LOCKED output of the PLL using a slice FF. Use this registered LOCKED signal as you would the LOCK output of the BUFPLL. This signal will be very similar to the correct behavior of LOCK. Designs with multiple BUFPLLs for multiple banks will commonly combine LOCK signals to ensure operation does not begin until all banks have properly locked.
• Contact Xilinx Technical Support for additional options: www.support.xilinx.com

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