If I use thePlanAhead RTL flow or Synplify Pro for synthesis, the Post-Translate simulation model generated from Netgen causes the following error on "X_RAM32M" or "X_RAM64M"in ModelSim simulation:
"Error: xxxxx/top.v(1143): (vopt-2135) Too many port connections. Expected 14, found 34."
This is because the"X_RAM32M" or "X_RAM64M" instantiation has ports for each port bit. In the following example, ADDRA is a port of 6-bit width whichhas been split as ADDRA,ADDRA, ADDRA, ADDRA , ADDRA and ADDRA:
.INIT_A ( 64'h0000000000000000 ),
.INIT_B ( 64'h0000000000000000 ),
NOTE:This issue only occurs in designs that contain Distributed RAM.
This error only occurs if the Synthesized netlist is of EDIF format. If the netlist is of NGC format, Netgen will generate the correct simulation model.
To work around this issue, use either of the following methods: