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AR# 45052

13.3 Netgen - The Post-Translate simulation model has port mismatch error when using PlanAhead RTL flow or Synplify Pro

Description

If I use thePlanAhead RTL flow or Synplify Pro for synthesis, the Post-Translate simulation model generated from Netgen causes the following error on "X_RAM32M" or "X_RAM64M"in ModelSim simulation:

"Error: xxxxx/top.v(1143): (vopt-2135) Too many port connections. Expected 14, found 34."


This is because the"X_RAM32M" or "X_RAM64M" instantiation has ports for each port bit. In the following example, ADDRA is a port of 6-bit width whichhas been split as ADDRA[5],ADDRA[4], ADDRA[3], ADDRA[2] , ADDRA[1] and ADDRA[0]:

X_RAM64M #(
.INIT_A ( 64'h0000000000000000 ),
.INIT_B ( 64'h0000000000000000 ),
......

.\ADDRA[5] (addr_5_IBUF_89),
.\ADDRA[4] (addr_4_IBUF_90),
.\ADDRA[3] (addr_3_IBUF_91),
.\ADDRA[2] (addr_2_IBUF_92),
.\ADDRA[1] (addr_1_IBUF_93),
.\ADDRA[0] (addr_0_IBUF_94),
......

);

NOTE:This issue only occurs in designs that contain Distributed RAM.

Solution

This error only occurs if the Synthesized netlist is of EDIF format. If the netlist is of NGC format, Netgen will generate the correct simulation model.

To work around this issue, use either of the following methods:

  • Use the ISE flow and XST as the Synthesizer.
  • Run Post-MAP or Post-PAR simulation instead of Post-Translate simulation. The Post-MAP and Post-PAR simulation models do not have this issue.
This issue has been fixed in ISE Design Suite 13.4.
AR# 45052
Date Created 03/02/2012
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • PlanAhead - 12.1
  • PlanAhead - 12.2
  • PlanAhead - 12.3
  • More
  • PlanAhead - 12.4
  • PlanAhead - 13.1
  • PlanAhead - 13.2
  • PlanAhead - 13.3
  • Less