AR# 45056


LogiCORE IP Serial RapidIO Gen2 v1.2 - Idle_selected signal is Hi-Z in simulation


When I simulateLogiCORE IP Serial RapidIO Gen2 v1.2 example design, the signal "idle_selected" is Hi-Z.


This is a known issue that is to be fixed in v1.3 release of the core.

Revision History

1/9/2012- Initial release

AR# 45056
Date 05/19/2012
Status Archive
Type Known Issues
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