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LogiCORE IP Serial RapidIO Gen2 v1.2 - Idle_selected signal is Hi-Z in simulation
When I simulateLogiCORE IP Serial RapidIO Gen2 v1.2 example design, the signal "idle_selected" is Hi-Z.
This is a known issue that is to be fixed in v1.3 release of the core.
1/9/2012- Initial release
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