2. Support
  3. AR# 4516: Installing A1.5 using SUNOS is not supported.
  4. AR# 45166: Design Advisory for Virtex-6 FPGA GTH Transceiver - Incorrect RX_P1_CTRL attribute can cause undesirable RX behavior

AR# 45166

Design Advisory for Virtex-6 FPGA GTH Transceiver - Incorrect RX_P1_CTRL attribute can cause undesirable RX behavior

Description

In the Virtex-6 FPGA GTH Transceiver, there are several types of undesirable RX behavior that can be caused by an incorrect setting of RX_P1_CTRL attribute. This answer record describes the various symptoms that can be exhibited and the correct setting to address them.

Solution

Symptom 1

Lane 0 powerdown can cause burst of errors to Lane 1 in the same quad and vice versa. Lane 2 powerdown can cause burst of errors in Lane 3 of the same Quad and vice versa. The interaction is seen when the circuit comes out of reset. Lane 2and 3 have the same interaction. Other Quads are not affected.

When resetting each receiver independently through the Wizard pin 'quad*_rx_pcs_cdr_reset*_i' signal assertion, this drives the Lane powerdown and for this reason, it causes burst of errors on other Lanes. The same effect can be seen by toggling the pin POWERDOWN and RXPOWERDOWN on the channel.

Symptom 2

In some cases when resetting the receiver through the Wizard port 'RX_PCS_CDR_RESET_IN' or toggling the GTH's RXPOWERDOWN port, the RX recovered clock might stay flatlined. As a result, RX_PCS_CDR_RESETDONE_OUT might not assert High after a reset.

Symptom 3

When the RX data at the GTH is lost and regained due to situations such as remote link powering up, disconnecting and reconnecting the RXP/RXN serial pins, the GTH may not recover properly if only a RX reset sequence is performed through the Wizard port 'RX_PCS_CDR_RESET_IN' or toggling the GTH's RXPOWERDOWN port.

Solution

All the above symptoms can be avoided by using the following work-around:

  • On DRP address 6016, there is an attribute RX_P1_CTRL. Set this attribute to 16'h0216.
  • This attribute update must be put into the actual HDL code or UCF followed by generating a new bit file.

Revision History
04/05/2013 - Updated the title, added symptom 3 and updated the value from 16'h1216 to 16'h0216
01/13/2012 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34565 Design Advisory Master Answer Record for Virtex-6 FPGA N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
38596 Virtex-6 FPGA GTH Transceiver - Known Issues and Answer Records List N/A N/A
AR# 45166
Date 04/05/2013
Status Active
Type Design Advisory
Devices