General Information
The MIG Virtex-6 and Spartan-6 v3.91 products are available through the ISE Design Suite 13.4. For a list of supported memory interfaces and frequencies for the Spartan-6 FPGA Memory Controller Block (MCB), see the following user guides:
For a list of supported memory interfaces and frequencies for Virtex-6 FPGA, see the following documentation:
For general design and troubleshooting information on MIG, see (Xilinx Answer 34243) for the Xilinx MIG Solution Center.
Software Requirements
New Features
Resolved Issues
Known Issues
Virtex-6
Spartan-6
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
45765 | MIG v3.91 Virtex-6 DDR3/DDR2 - 72-bit and 144-bit AXI Lite designs fail in simulation using ModelSim | N/A | N/A |
47721 | MIG v3.91 Virtex-6 QDRII+ - Initialization sequence incorrect for Cypress parts | N/A | N/A |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
45765 | MIG v3.91 Virtex-6 DDR3/DDR2 - 72-bit and 144-bit AXI Lite designs fail in simulation using ModelSim | N/A | N/A |
38731 | MIG v3.5-v3.91, Virtex-6 DDR3 - Simulation - 'SKIP' Calibration Causes Errors in the Example Design | N/A | N/A |
39423 | MIG v3.6-v3.91 Virtex-6 DDR2/DDR3/QDRII+ - The VRN/VRP pins were occupied by controller I/Os which require another bank for DCI Cascade | N/A | N/A |
38623 | MIG Spartan-6 MCB - Why is ODT issued late by the MCB when operating in DDR2 mode 400 Mbps? | N/A | N/A |
47721 | MIG v3.91 Virtex-6 QDRII+ - Initialization sequence incorrect for Cypress parts | N/A | N/A |